In general, a DLL (delay locked loop) circuit functions to delay a reference clock signal by a preset time period to thereby generate a delayed clock signal which is delayed relative to the reference clock signal. The generation of delayed clock signals is generally necessary in certain circuits which exhibit relatively high integration densities and which are synchronized with external clock signals. Such circuits include DRAM (dynamic random access memory) integrated circuit device.
For example, a semiconductor memory device that operates in synchronization with an external clock signal will receive the external clock signal via an input pin of the integrated circuit device, which is applied to a clock buffer to generate an internal clock signal. The internal clock signal, in turn, controls, e.g., a data output buffer to output data from the integrated circuit memory device. If the internal clock signal is delayed by a predetermined time from the external clock signal, high-frequency operation performance of the memory device is degraded. In particular, the data output time after the external clock signal is applied, i.e., output data access time (tAC), is increased. In other words, due to the delay, the time period needed to output data (output data access time) is increased. Accordingly, a DLL can be implemented in the semiconductor integrated circuit memory device to facilitate synchronization of memory access functions.
FIG. 1A schematically illustrates a conventional embodiment of a delay locked loop (DLL). The DLL circuit (100) comprises a phase detector (10), delay controller (20), delay unit (30) and compensation delay unit (40). In general, the delay unit (30) delays the external clock signal (XCLK) under control of the delay controller (20) to generate a delayed clock signal (XDATA). The delayed clock signal (XDATA) is used as a reference signal for, e.g., synchronizing data output with the rising edge of the external clock signal (XCLK) (i.e., the DLL (100) serves to make the access time (tAC)=0).
The output of the DLL (100) (i.e., the delayed signal (XDATA) is fed back to the compensation delay unit (40), which generates a feedback signal (FBI). The phase detector (10) (or phase comparator) compares the phase of the external clock signal (XCLK) with the phase of the feedback signal (FBI) and generates a detection signal that corresponds to a detected phase difference between the external clock signal (XCLK) and the feedback signal (FBI). The detection signal is input to the delay controller (20), which then generates a control signal based on the detection signal to control the delay unit (30) to vary (increase or decrease) the amount of delay that is applied to the external clock signal (XCLK).
The conventional DLL (100) of FIG. 1A is configured such that the delay unit can only make relatively large coarse adjustments (e.g., several picoseconds). However, when finer delay adjustability is required for high-frequency operation, the DLL architecture of FIG. 1B may be implemented.
In particular, FIG. 1B schematically illustrates a conventional DLL circuit (200), which implements a coarse-lock/fine-lock scheme. Referring to FIG. 1B, the DLL (200) is similar to the DLL (100) of FIG. 1A in that the DLL (200) includes a phase detector (10), a delay controller (20) and a compensation delay unit (40). However, the DLL (200) comprises a coarse-lock delay unit (50) and a fine-lock delay unit (60). The phase detector (10) compares the external clock signal (XCLK) with the feedback signal (FBI) from the compensation delay unit (40) to generate detection (comparison) signals corresponding to detected phase differences between the external clock signal (XCLK) and the feedback signal (FBI). The delay controller (20) receives the detection signals and generates either a first delay control signal or a second delay control signal.
The coarse-lock delay unit (50) is responsive to the first delay control signal to delay the external clock signal (XCLK) by a predetermined first phase delay. The fine-lock delay unit (60) is responsive to the second delay control signal to delay the external clock signal (XCLK) by a predetermined second phase delay (which is smaller than the first phase delay)). More specifically, the coarse-lock delay unit (50) provides phase delay increments that are greater that the phase delay increments provided by the fine-lock delay unit (60). The coarse-lock delay unit (50) operates to coarsely adjust the delay of the external clock signal (XCLK) at a higher speed, and the fine-lock delay unit (60) operates to finely adjust the delay of the external clock signal (XCLK) to generate the delayed clock signal (XDATA). The output of the DLL (200), i.e., the delayed signal (XDATA), is fed back to the compensation delay unit (40) to generate the feedback signal (FBI).
FIG. 2A is an exemplary timing diagram illustrating a condition in which the phase the feedback signal (FBI) lags behind the phase of the external clock signal (XCLK) and FIG. 2B is an exemplary timing diagram illustrating a condition in which the phase of the feedback signal (FBI) leads the phase of the external clock signal (XCLK). With the condition depicted in FIG. 2A, the phase of the delayed output signal (XDATA) lags that of the external clock signal, and the delay controller (20) generates control signal to increase phase delay applied to the external clock signal (XCLK) to generate the output signal (XDATA). On the other hand, with the condition depicted in FIG. 2B, the phase of the delayed output signal (XDATA) leads that of the external clock signal, and the delay controller (20) generates a control signal to decrease the phase delay applied to the external clock signal (XCLK) to generate the output signal (XDATA).
In a delay locked loop (DLL) using a coarse-lock/fine-lock architecture such as depicted in FIG. 1B, a mechanism is provided for determining when to transition from the coarse-lock to the fine-lock delay. One method for determining when to transition from coarse-lock to fine-lock is detecting a condition in which the phase of the feedback signal (FBI) is initially detected (at one point in time) to lag behind the phase of the external clock signal (XCLK) and then the phase of the feedback signal (FBI) is subsequently detected (at the next point in time) to lead the phase of the external clock signal (XCLK). When this condition occurs, the coarse-lock transitions to the fine-lock delay.
For example, the exemplary timing diagrams of FIGS. 3A and 3B illustrate a method for determining when to transition from a coarse-lock to a fine-lock in the conventional DLL circuit (200) of FIG. 1B. FIG. 3A illustrates an initial point in time in which the phase detector (10) compares the phase difference between the feedback signal (FBI) and the external clock signal (XCLK) by detecting the logic value of the external clock signal (XCLK) at a rising edge of the feedback signal (FBI). In FIG. 3A, the logic level of the external clock signal (XCLK) is determined to be logic low “L” at that time (i.e., the phase of the data output lags behinds a phase of the external clock signal (XCLK)). As with the method of FIG. 2A, the delay of the output signal (XDATA) will be increased.
FIG. 3B illustrates the next point in time in which the phase detector (10) compares the phase difference between the feedback signal (FBI) and the external clock signal (XCLK) by detecting the logic value of the external clock signal (XCLK) at a rising edge of the feedback signal (FBI). In FIG. 3B, the logic level of the external clock signal (XCLK) is determined to be logic low “H” at that time (i.e., the phase of the data output leads the phase of the external clock signal (XCLK)). When this condition (L→H) is detected for two successive detection times (i.e., the phase of the feedback signal (FBI) first lags and then leads the phase of the external clock signal (XCLK)), the DDL transitions from the coarse-lock control to the fine-lock control.
FIG. 4 is a block diagram illustrating a conventional embodiment of the phase detector (10), which comprises a comparator (15) which receives as input the feedback signal (FBI) and the external clock signal (XCLK) and outputs as a detection signal (FBO) the logic level of the external clock signal (XCLK) at the rising edge of the feedback signal (FBI).
FIG. 5 is an exemplary timing diagram to illustrate a condition in which the phase detector (10) in the conventional DLL (200) can malfunction by incorrectly transitioning from a coarse-lock delay unit to the fine-lock delay unit due to the occurrence of jitter or noise. As depicted in the exemplary timing diagram of FIG. 5, a situation may occur whereby the feedback signal (FBI) is compared to the external clock signal (XCLK) in the phase detector (10) at a first time when the rising edge of the feedback signal (FBI) is positioned on a low level around the falling edge of the external clock signal (XCLK) (detection signal (FBO) is logic low “L”) and then at a next time goes to a high level, just after being compared with the external clock signal, due to a jittering of the external clock signal. In this case, the external clock signal should be transmitted to the fine-lock unit with, e.g., a half clock delay by the coarse-lock unit, but due to the jitter, the external clock signal is applied to the fine-lock unit without the half clock delay. As a result, there is a malfunction. Since the jitter of the external clock signal is typically ±5%, the noise immunity of the conventional DLL suffering from such a malfunction is considerably weakened.